Langganan:
Posting Komentar (Atom)
skip to main |
skip to sidebar
Pengikut
Arsip Blog
-
▼
2010
(36)
-
▼
Januari
(36)
- single vs multi cycle processor 2
- private and shared L2 cache
- fine-grained and simultaneous multithreading
- multithreading
- lock
- M E S I
- contoh snooping
- cache coherence protocol
- Distributed Memory Multiprocessors
- SMP
- taxonomy multiprocessor
- RAID
- polling vs interupt-driven
- DMA
- bus design
- TLB
- Memory Hierarchy Properties
- virtual memory
- type of cache misses
- cache misses
- write
- aspek cache
- control hazard 2
- structural hazard 2
- hazard
- hierarki memory
- data hazard
- control hazard
- structural hazard
- jenis hazard
- Keuntungan sistem Pipeline
- keuntungan multi cycle-processor v single no 9
- keuntungan d-latch
- operasi 1 bit ALU
- Hukum De Morgan no 1
- PEMBUKTIAN HUKUM DE MORGAN (a.b)' = a' +b'
-
▼
Januari
(36)
Tidak ada komentar:
Posting Komentar